An Area and Power Efficient Reconfigurable Processor for Binary Image Processing

Binary image processing is a powerful tool in many image and video applications. This paper describes A reconfigurable processor for binary image processing. Reconfigurable binary image processing chips have been designed mainly for the binary image applications of a chip. The processor architecture is designed for input output control unit, reconfigurable binary processing module, and peripheral circuits. The reconfigurable binary compute units is a mixed grained architecture, which has the important features of high flexibility, efficiency, and performance. The dynamic reconfiguration approach supports the performance of the processor. The mixed-grained architecture reconfigurable binary compute units and output control logic are the important functional blocks of the reconfigurable binary processing module , performs binary image processing operations, especially mathematical morphology operations. The Chips were designed to perform specially basic binary morphological operations, like dilation, erosion, opening, and closing and other powerful image processing applications.The chips also designed with filtering operations such as FIR and IIR operations.Here we using the Dual Edge trigerring technique to support low power consumption and replaces the DDRSDRAM instead of SDRAM to increase the execution speed. This Processor architecture has been successfully synthesized and implemented using Xilinx ISE DS 13.2.2.We have implemented the Reconfigurable architecture in VHDL through FPGA using Xilinx ISE design suite 13.2.2.